#ifndef __CSP_NVIC_H__
#define __CSP_NVIC_H__


//#include "AC33Mx128.h"

//==========================================================================
// SCS (System Control Space)
//
//					Address				Symbol		Type		Name 
//					--------------------------------------------------------------------------
//					0xE000_E004			ICTR		RO			Interrupt Control Type Register
//					0xE000_E008			ACR			R/W			Auxiliary Control Register
//
//==========================================================================
typedef struct {
	CSP_REGISTER_T		res0;
	CSP_REGISTER_T		ICTR;
	CSP_REGISTER_T		ACR;
} CSP_SCS_T; 




//==========================================================================
// SysTick (System Timer)
//
//					Address				Symbol		Type		Name 
//					--------------------------------------------------------------------------
//					0xE000_E010			CSR			RW			SysTick Control and Status Register
//					0xE000_E014			RVR			R/W			SysTick Reload Value Register
//					0xE000_E018			CVR			R/WC		SysTick Current Value Register
//					0xE000_E01C			CALIB		RO			SysTick Calibration Value Register 
//
//==========================================================================
typedef struct {
	CSP_REGISTER_T		CSR;
	CSP_REGISTER_T		RVR;
	CSP_REGISTER_T		CVR;
	CSP_REGISTER_T		CALIB;
} CSP_SYSTICK_T; 



//==========================================================================
// NVIC (Nested Vectored Interrupt Controller)
//
//
//			Address						Symbol		Type		Name 
//			--------------------------------------------------------------------------
//			0xE000_E100~0xE000_E11F		ISER		RW			Interrupt Set Enable Register
//			0xE000_E180~0xE000_E19F		ICER		RW			Interrupt Clear Enable Register 
//			0xE000_E200~0xE000_E21F		ISPR		RW			Interrupt Set Pending Register
//			0xE000_E280~0xE000_E29F		ICPR		RW			Interrupt Clear Pending Register 
//			0xE000_E300~0xE000_E31F		IABR		R			Interrupt Active Bit Register
//			0xE000_E400~0xE000_E4EF		IPR			RW			Interrupt Priority Register (8 bits)
//
//==========================================================================
typedef struct {
	CSP_REGISTER_T		ISER[8];
	CSP_REGISTER_T		res0[24];

	CSP_REGISTER_T		ICER[8];
	CSP_REGISTER_T		res1[24];

	CSP_REGISTER_T		ISPR[8];
	CSP_REGISTER_T		res2[24];	

	CSP_REGISTER_T		ICPR[8];
	CSP_REGISTER_T		res3[24];	

	CSP_REGISTER_T		IABR[8];
	CSP_REGISTER_T		res4[56]; 

	CSP_REGISTER8_T		IPR[240]; 

} CSP_NVIC_T; 


//==========================================================================
// SCB (System Control Block)
//
//
//					Address				Symbol		Type		Name 
//					--------------------------------------------------------------------------
//					0xE000_ED00			CPUID		R			CPUID Base Register
//					0xE000_ED04			ICSR		RW			Interrupt Control Status Register
//					0xE000_ED0C			AIRCR		RW			Application 
//
//					0xE000_ED10			SCR			RW			System Control Reigster
//					0xE000_ED14			CCR			RW			Configuration Control Register 
//					0xE000_ED1C			SHPR1		RW			System Handlers 8-11 Priority Register
//
//					0xE000_ED20			SHPR2		RW			System Handlers 12-15 Priority Reigster
//
//==========================================================================
//
//					PAGE 445
//
//==========================================================================
typedef struct {
	CSP_REGISTER_T		CPUID;				// addr = 0xE000_ED00
	CSP_REGISTER_T		ICSR;				// addr = 0xE000_ED04
	CSP_REGISTER_T		res08; 				// addr = 0xE000_ED08
	CSP_REGISTER_T		AIRCR; 				// addr = 0xE000_ED0c

	CSP_REGISTER_T		SCR;				// addr = 0xE000_ED10
	CSP_REGISTER_T		CCR; 				// addr = 0xE000_ED14
	CSP_REGISTER_T		res18;				// addr = 0xE000_ED18
	CSP_REGISTER_T		SHPR2; 				// addr = 0xE000_ED1C
	
	CSP_REGISTER_T		SHPR3; 				// addr = 0xE000_ED20
	CSP_REGISTER_T		SHCSR; 				// addr = 0xE000_ED24


} CSP_SCB_T; 

#if 0 
typedef struct {
	CSP_REGISTER_T		CPUID;				// 0xE000_ED00
	CSP_REGISTER_T		ICSR;
	CSP_REGISTER_T		VTOR; 
	CSP_REGISTER_T		AIRCR; 

	CSP_REGISTER_T		SCR;				// 0xE000_ED10
	CSP_REGISTER_T		CCR; 
	CSP_REGISTER_T		SHPR[3];

	CSP_REGISTER_T		SHCSR; 				// 0xE000_ED24
	CSP_REGISTER_T		CFSR;				
	CSP_REGISTER_T		HFSR;
	
	CSP_REGISTER_T		DFSR;				// 0xE000_ED30
	CSP_REGISTER_T		MMAR;
	CSP_REGISTER_T		BFAR;
	CSP_REGISTER_T		AFSR;

	CSP_REGISTER_T		PFR0;				// 0xE000_ED40
	CSP_REGISTER_T		PFR1;
	CSP_REGISTER_T		DFR0;
	CSP_REGISTER_T		AFR0;

	CSP_REGISTER_T		MMFR0;				// 0xE000_ED50
	CSP_REGISTER_T		MMFR1;
	CSP_REGISTER_T		MMFR2;
	CSP_REGISTER_T		MMFR3; 

	CSP_REGISTER_T		ISAR0; 				// 0xE000_ED60
	CSP_REGISTER_T		ISAR1; 
	CSP_REGISTER_T		ISAR2; 
	CSP_REGISTER_T		ISAR3; 

	CSP_REGISTER_T		ISAR4; 				// 0xE000_ED70
	CSP_REGISTER_T		res0[3];

	CSP_REGISTER_T		res1[32];			// 0xE000_ED80 ~ 0xE000_EDFF

	CSP_REGISTER_T		STIR;				// 0xE000_EF00

} CSP_SCB_T; 
#endif 



//==========================================================================
// TPIU (Trace Port Interface Unit)
//
//
//					Address				Symbol		Type		Name 
//					--------------------------------------------------------------------------
//					0xE004_0000			SSPSR		RO			Supported Sync Port Size Register
//					0xE004_0004			CSPSR		RW			Current Sync Port Size Register
//					0xE004_0010			ACPR		RW			Async Clock Prescaler Register
//					0xE004_00F0			SPPR		RW			Selected Pin Protocol Register
//
//==========================================================================
//
//					PAGE 445
//
//==========================================================================
typedef struct {
	CSP_REGISTER_T		SSPSR;				// addr = 0xE004_0000
	CSP_REGISTER_T		CSPSR;				// addr = 0xE004_0004
	CSP_REGISTER_T		res08; 				// addr = 0xE004_0008
	CSP_REGISTER_T		res0C; 				// addr = 0xE004_000C

	CSP_REGISTER_T		ACPR;				// addr = 0xE004_0010
	CSP_REGISTER_T		res14; 				// addr = 0xE004_0014
	CSP_REGISTER_T		res18;				// addr = 0xE004_0018
	CSP_REGISTER_T		res1C; 				// addr = 0xE004_001C
	
	CSP_REGISTER_T		res20_EF[4*13]; 	// addr = 0xE004_0020~0xE004_00EC
	CSP_REGISTER_T		SPPR; 				// addr = 0xE004_00F0


} CSP_TPIU_T; 




//##########################################################################
//#
//#		Data Structure 
//#
//##########################################################################
//---------------------------------------------------------------------------------------
// Vecotr Table Number : 1~15
//
//			nException_Number		Vector Name
//			----------------		-----------
//				-1					Reset
//				-2					NMI
//				-3					Hard Fault
//				-4					Memeory Manage
//				-5					Bus Fault
//				-6					Usage Fault
//
//				-11					SVCall
//				-12					Debug Monitor
//				
//				-14					PendSV
//				-15					SysTick 
//
//---------------------------------------------------------------------------------------
typedef struct {
	int		nException_Number;
	UINT8	u8Preemption_Priority;
	UINT8	u8Subpriority;
	UINT8	u8ExceptionEnable;
} SCB_ExceptionConfig; 


//---------------------------------------------------------------------------------------
// Vecotr Table Number : 16~239
//---------------------------------------------------------------------------------------
typedef struct {
	int		nIRQ_Number;
	UINT8	u8Preemption_Priority;
	UINT8	u8Subpriority;
	UINT8	u8IntrEnable;
} NVIC_IntrConfig; 



//##########################################################################
//#
//#		Vector Number (0~15)
//#
//##########################################################################
#define VECT_NUM_RESET					(1)
#define VECT_NUM_NMI					(2)
#define VECT_NUM_HARD_FAULT				(3)

#define VECT_NUM_MEMORY_MANAGE			(4)
#define VECT_NUM_BUS_FAULT				(5)
#define VECT_NUM_USAGE_FAULT			(6)

#define VECT_NUM_SVCALL					(11)
#define VECT_NUM_DEBUG_MONITOR			(12)

#define VECT_NUM_PENDSV					(14)
#define VECT_NUM_SYSTICK				(15)
//-------------------------------------------------------------------------------------------

// System Exceptions
#define SYS_EXCEPT_RESET				(-1)
#define SYS_EXCEPT_NMI					(-2)
#define SYS_EXCEPT_HARD_FAULT			(-3)

#define SYS_EXCEPT_MEMORY_MANAGE		(-4)
#define SYS_EXCEPT_BUS_FAULT			(-5)
#define SYS_EXCEPT_USAGE_FAULT			(-6)

#define SYS_EXCEPT_SVCALL				(-11)
#define SYS_EXCEPT_DEBUG_MONITOR		(-12)

#define SYS_EXCEPT_PENDSV				(-14)
#define SYS_EXCEPT_SYSTICK				(-15)



//##########################################################################
//#
//#		IRQ number 
//#
//##########################################################################
#define IRQ_LVDFAIL						(0)
#define IRQ_SYSCLKFAIL					(1)
#define IRQ_XOSCFAIL					(2)
#define IRQ_WDT							(3)
// NULL									(4)
#define IRQ_TIMER0						(5)
#define IRQ_TIMER1						(6)
#define IRQ_TIMER2						(7)
#define IRQ_TIMER3						(8)
// NULL									(9)
// NULL									(10)
// NULL									(11)
// NULL									(12)
#define IRQ_TIMER8						(13)
#define IRQ_TIMER9						(14)
// NULL									(15)
#define	IRQ_GPIOAE						(16)
#define	IRQ_GPIOAO						(17)
#define	IRQ_GPIOBE						(18)
#define	IRQ_GPIOBO						(19)
#define	IRQ_GPIOCE						(20)
#define	IRQ_GPIOCO						(21)
#define	IRQ_GPIODE						(22)
#define	IRQ_GPIODO						(23)
#define IRQ_MPWM0						(24)
#define IRQ_MPWM0PROT					(25)
#define IRQ_MPWM0OVV					(26)
#define IRQ_MPWM1						(27)
#define IRQ_MPWM1PROT					(28)
#define IRQ_MPWM1OVV					(29)
//NULL									(30)
//NULL									(31)
#define IRQ_SPI0						(32)
#define IRQ_SPI1						(33)
//NULL									(34)
//NULL									(35)
#define IRQ_I2C0						(36)
#define IRQ_I2C1						(37)
#define IRQ_UART0						(38)
#define IRQ_UART1						(39)
#define IRQ_UART2						(40)
#define IRQ_UART3						(41)
// NULL									(42)
#define IRQ_ADC0						(43)
#define IRQ_ADC1						(44)
#define IRQ_ADC2						(45)
#define IRQ_COMP0						(46)
#define IRQ_COMP1						(47)
#define IRQ_COMP2						(48)
#define IRQ_COMP3						(49)


#define AC33M8128_IRQ_NUM				(50)



//##########################################################################
//#
//#		Priority 
//#
//##########################################################################
//-----------------------------------------------------------------------------------
// Priority Mask
//
//				MC33F364 supports only the upper three bits, whis is the most
//				popular scheme.
//
//-----------------------------------------------------------------------------------
#define START_BITPOS_OF_PRIORITY				(5)
#define PRIORITY_MASK							(0x07<<5)


//-----------------------------------------------------------------------------------
// PRIORITY_GROUP_VALUE = 4
//
//				preemption priority					bit 7-5
//				subpriority						none 
//
//
// PRIORITY_GROUP_VALUE = 5
//
//				preemption priority					bit 7-6
//				subpriority						bit 5 
//
//
// PRIORITY_GROUP_VALUE = 6
//
//				preemption priority					bit 7
//				subpriority						bit 6-5 
//
//
// PRIORITY_GROUP_VALUE = 7
//
//				preemption priority					none
//				subpriority						bit 7-5 
//
//-----------------------------------------------------------------------------------
//#define PRIORITY_GROUP_VALUE					(4)
//#define PREEMPTION_MASK						(0x07<<5)
//#define SUBPRIORITY_MASK						(0x00<<5)


//#define PRIORITY_GROUP_VALUE					(5)
//#define PREEMPTION_MASK						(0x03<<6)
//#define SUBPRIORITY_MASK						(0x01<<5)


#define PRIORITY_GROUP_VALUE					(6)
#define PREEMPTION_MASK							(0x01<<7)
#define SUBPRIORITY_MASK						(0x03<<5)


//#define PRIORITY_GROUP_VALUE					(7)
//#define PREEMPTION_MASK						(0x00<<8)
//#define SUBPRIORITY_MASK						(0x07<<5)



//##########################################################################
//#
//#		Interrupt Enable/Disable 
//#
//##########################################################################
#define INTR_ENABLE								(1)
#define INTR_DISABLE							(0)

#define EXCEPTION_ENABLE						(1)
#define EXCEPTION_DISABLE						(0)



//==========================================================================
//#define PRIORITY_GROUP_VALUE			(6)
//#define PREEMPTION_MASK				(0x01<<7)
//#define SUBPRIORITY_MASK				(0x03<<5)
//==========================================================================
// IRQ0 - LVDFAIL 
#define PRIO_LVDFAIL_PREEMPTION			(1)
#define PRIO_LVDFAIL_SUBPRIORITY		(3)

// IRQ1 - SYSCLKFAIL
#define PRIO_SYSCLKFAIL_PREEMPTION		(1)
#define PRIO_SYSCLKFAIL_SUBPRIORITY		(3)

// IRQ2 - XOSCFAIL
#define PRIO_XOSCFAIL_PREEMPTION		(1)
#define PRIO_XOSCFAIL_SUBPRIORITY		(3)


// IRQ3 - WDT 
#define PRIO_WDT_PREEMPTION				(1)
#define PRIO_WDT_SUBPRIORITY			(3)

// IRQ4 - NULL

// IRQ5 - TIMER0
#define PRIO_TIMER0_PREEMPTION			(1)
#define PRIO_TIMER0_SUBPRIORITY			(3)

// IRQ6 - TIMER1
#define PRIO_TIMER1_PREEMPTION			(1)
#define PRIO_TIMER1_SUBPRIORITY			(3)

// IRQ7 - TIMER2
#define PRIO_TIMER2_PREEMPTION			(1)
#define PRIO_TIMER2_SUBPRIORITY			(3)

// IRQ8 - TIMER3
#define PRIO_TIMER3_PREEMPTION			(1)
#define PRIO_TIMER3_SUBPRIORITY			(3)

// IRQ9 - NULL
// IRQ10 - NULL
// IRQ11 - NULL
// IRQ12 - NULL

// IRQ13 - TIMER8
#define PRIO_TIMER8_PREEMPTION			(1)
#define PRIO_TIMER8_SUBPRIORITY			(3)

// IRQ14 - TIMER9
#define PRIO_TIMER9_PREEMPTION			(1)
#define PRIO_TIMER9_SUBPRIORITY			(3)

// IRQ15 - NULL

// IRQ16 - GPIOAE
#define PRIO_GPIOAE_PREEMPTION			(1)
#define PRIO_GPIOAE_SUBPRIORITY			(3)

// IRQ17 - GPIOAO
#define PRIO_GPIOAO_PREEMPTION			(1)
#define PRIO_GPIOAO_SUBPRIORITY			(3)

// IRQ18 - GPIOBE
#define PRIO_GPIOBE_PREEMPTION			(1)
#define PRIO_GPIOBE_SUBPRIORITY			(3)

// IRQ19 - GPIOBO
#define PRIO_GPIOBO_PREEMPTION			(1)
#define PRIO_GPIOBO_SUBPRIORITY			(3)

// IRQ20 - GPIOCE
#define PRIO_GPIOCE_PREEMPTION			(1)
#define PRIO_GPIOCE_SUBPRIORITY			(3)

// IRQ21 - GPIOCO
#define PRIO_GPIOCO_PREEMPTION			(1)
#define PRIO_GPIOCO_SUBPRIORITY			(3)

// IRQ22 - GPIODE
#define PRIO_GPIODE_PREEMPTION			(1)
#define PRIO_GPIODE_SUBPRIORITY			(3)

// IRQ23 - GPIODO
#define PRIO_GPIODO_PREEMPTION			(1)
#define PRIO_GPIODO_SUBPRIORITY			(3)

// IRQ24 - MPWM0
#define PRIO_MPWM_PREEMPTION			(1)
#define PRIO_MPWM_SUBPRIORITY			(3)

// IRQ25 - MPWM0PROT
#define PRIO_MPWMPROT_PREEMPTION		(1)
#define PRIO_MPWMPROT_SUBPRIORITY		(3)

// IRQ26 - MPWM0OVV
#define PRIO_MPWMOVV_PREEMPTION			(1)
#define PRIO_MPWMOVV_SUBPRIORITY		(3)

// IRQ27 - MPWM1
#define PRIO_MPWM_PREEMPTION			(1)
#define PRIO_MPWM_SUBPRIORITY			(3)

// IRQ28 - MPWM1PROT
#define PRIO_MPWMPROT_PREEMPTION		(1)
#define PRIO_MPWMPROT_SUBPRIORITY		(3)

// IRQ29 - MPWM1OVV
#define PRIO_MPWMOVV_PREEMPTION			(1)
#define PRIO_MPWMOVV_SUBPRIORITY		(3)

// IRQ30 - NULL
// IRQ31 - NULL

// IRQ32 - SPI0
#define PRIO_SPI0_PREEMPTION			(1)
#define PRIO_SPI0_SUBPRIORITY			(3)

// IRQ33 - SPI1
#define PRIO_SPI1_PREEMPTION			(1)
#define PRIO_SPI1_SUBPRIORITY			(3)

// IRQ34 - NULL
// IRQ35 - NULL

// IRQ36 - I2C0
#define PRIO_I2C0_PREEMPTION			(1)
#define PRIO_I2C0_SUBPRIORITY			(3)

// IRQ37 - I2C1
#define PRIO_I2C1_PREEMPTION			(1)
#define PRIO_I2C1_SUBPRIORITY			(3)

// IRQ38 - UART0
#define PRIO_UART0_PREEMPTION			(1)
#define PRIO_UART0_SUBPRIORITY			(3)

// IRQ39 - UART1
#define PRIO_UART1_PREEMPTION			(1)
#define PRIO_UART1_SUBPRIORITY			(3)

// IRQ40 - UART2
#define PRIO_UART2_PREEMPTION			(1)
#define PRIO_UART2_SUBPRIORITY			(3)

// IRQ41 - UART3
#define PRIO_UART3_PREEMPTION			(1)
#define PRIO_UART3_SUBPRIORITY			(3)

// IRQ42 - NULL

// IRQ43 - ADC0
#define PRIO_ADC0_PREEMPTION			(1)
#define PRIO_ADC0_SUBPRIORITY			(3)

// IRQ44 - ADC1
#define PRIO_ADC1_PREEMPTION			(1)
#define PRIO_ADC1_SUBPRIORITY			(3)

// IRQ45 - ADC2
#define PRIO_ADC2_PREEMPTION			(1)
#define PRIO_ADC2_SUBPRIORITY			(3)


// IRQ46 - COMP0
#define PRIO_COMP0_PREEMPTION			(1)
#define PRIO_COMP0_SUBPRIORITY			(3)

// IRQ47 - COMP1
#define PRIO_COMP1_PREEMPTION			(1)
#define PRIO_COMP1_SUBPRIORITY			(3)

// IRQ48 - COMP2
#define PRIO_COMP2_PREEMPTION			(1)
#define PRIO_COMP2_SUBPRIORITY			(3)

// IRQ49 - COMP3
#define PRIO_COMP3_PREEMPTION			(1)
#define PRIO_COMP3_SUBPRIORITY			(3)






//##########################################################################
//#
//#		SYSTEM CONTROL SPACE 
//#
//##########################################################################

//==========================================================================
// ICTR (Interrupt Control Type Register)
//
//					addr = 0xE000_E004
//
//==========================================================================
//
//					bit 4-0		INTLINESUM	
//								00000b = 0~32
//								00001b = 33~64
//								
//								00111b = 225~256
//
//==========================================================================
#define ICTR_INTLINESUM						(0x001F<<0)



//==========================================================================
// ACR (Auxiliary Control Register)
//
//					addr = 0xE000_E008
//
//==========================================================================
//
//					bit 2			DISFOLD
//								disables IT folding
//
//					bit 1			DISDEFWBUF
//								disables write buffer use during default memory map accesses
//
//					bit 0			DISMCYCINT
//								disables interruption of multi-cycle instructions. 
//
//==========================================================================
#define ACR_DISFOLD							(0x0001<<2)
#define ACR_DISDEFWBUF						(0x0001<<1)
#define ACR_DISMCYCINT						(0x0001<<0)





//##########################################################################
//#
//#		SYSTICK 
//#
//##########################################################################

//==========================================================================
// CSR (SysTick Control and Status Register)
//
//					addr = 0xE000_E010
//
//==========================================================================
//
//					bit 16		COUNTFLAG
//								1 = timer counted down to 0 since last read time
//
//					bit 2			CLKSOURCE
//								0 = external reference clock 
//								1 = core clock 
//
//					bit 1			TICKINT 
//								0 = disable interrupt 
//								1 = enable interrupt 
//
//					bit 0			ENABLE
//								0 = disable counter
//								1 = enable counter 
//
//==========================================================================
#define CSR_COUNTFLAG					(0x0001<<16)

#define CSR_CLKSOURCE 					(0x0001<<2)
#define CSR_CLKSOURCE_EXTREF_CLOCK		(0x0000<<2)
#define CSR_CLKSOURCE_CORE_CLOCK		(0x0001<<2)
#define CSR_TICKINT						(0x0001<<1)
#define CSR_ENABLE						(0x0001<<0)




//==========================================================================
// RVR (SysTick Reload Value Register)
//
//					addr = 0xE000_E014
//
//==========================================================================
//
//					bit 23-0		RELOAD 
//								
//==========================================================================
#define RVR_RELOAD_MASK					(0x00FFFFFF<<0)




//==========================================================================
// CVR (SysTick Current Value Register)
//
//					addr = 0xE000_E018
//
//==========================================================================
//
//					bit 23-0		CURRENT
//								Write to this register with any value to clear the register and
//								the COUNTFLAG to 0. (This does not cause SysTick exception.)
//
//
//==========================================================================
#define CVR_CURRENT_MASK				(0x00FFFFFF<<0)




//==========================================================================
// CALIB (SysTick Calibration Value Register)
//
//					addr = 0xE000_E01C
//
//==========================================================================
//
//					bit 31		NOREF
//								0 = external reference clock is available
//								1 = external reference clock is not available 
//
//					bit 30		SKEW
//								0 = the TENMS bit field is accurate
//								1 = the TENMS bit field is not accurate
//
//					bit 23-0		TENMS
//								Ten milisecond calibration value 
//
//==========================================================================
#define CALIB_NOREF						(0x0001UL<<31)
#define CALIB_SKEW						(0x0001UL<<30)
#define CALIB_TENMS_MASK				(0x00FFFFFFUL<<0)




//==========================================================================
// SysTick Parameters
//
//
//==========================================================================

#define ST_CORE_CLOCK						(0)
#define ST_EXTREF_CLOCK						(1)

#define ST_INTR_TICK						CSR_TICKINT




//##########################################################################
//#
//#		NVIC
//#
//##########################################################################

//==========================================================================
// ISER (Interrupt Set Enable Register)
//
//					addr = 0xE000_E100 ~ 0xE000_E11F
//
//==========================================================================



//==========================================================================
// ICER (Interrupt Clear Enable Register)
//
//					addr = 0xE000_E180 ~ 0xE000_E19F
//
//==========================================================================



//==========================================================================
// ISPR (Interrupt Set Pending Register)
//
//					addr = 0xE000_E200 ~ 0xE000_E21F
//
//==========================================================================



//==========================================================================
// ICPR (Interrupt Clear Pending Register)
//
//					addr = 0xE000_E280 ~ 0xE000_E29F
//
//==========================================================================



//==========================================================================
// IABR (Interrupt Active Bit Register)
//
//					addr = 0xE000_E300 ~ 0xE000_E31F
//
//==========================================================================



//==========================================================================
// IPR (Interrupt Priority Register)
//
//					addr = 0xE000_E400 ~ 0xE000_E4EF
//
//==========================================================================



//##########################################################################
//#
//#		SCB 
//#
//##########################################################################

//==========================================================================
// CPUID (CPUID Base Register)
//
//					addr = 0xE000_ED00
//
//==========================================================================
//
//					bit 31-24		IMPLEMENTER
//								0x41 = ARM
//
//					bit 23-20		VARIANT
//
//					bit 19-16		CONSTATNT
//								0x0F = fixed 
//
//					bit 15-4		PARTNO
//								[11:10]	11b 		= Cortex family
//								[9:8]	00b 		= version 
//								[7:6]	00b 		= reserved
//								[5:4]	10b 		= M
//								[3:0]	0011b	= Cortex-M3 family
//
//					bit 3-0		REVISION
//
//==========================================================================



//==========================================================================
// ICSR (Interrupt Control State Register)
//
//					addr = 0xE000_ED04
//
//==========================================================================
//
//					bit 31		NMIPENDSET (RW)
//								0 = do not set pending NMI
//								1 = set pending NMI
//
//
//					bit 28		PENDSVSET (RW)
//								0 = do not set pending PendSV
//								1 = set pending PendSV
//
//					bit 27		PENDSVCLR (WO)
//								0 = do not clear pending PendSV
//								1 = clear pending PendSV
//
//
//					bit 26		PENDSTSET (RW)
//								0 = do not set pending SysTick
//								1 = set pending SysTick
//
//					bit 25		PENDSTCLR (WO)
//								0 = do not clear pending SysTick
//								1 = clear pending SysTick 
//
//
//					bit 23		ISRPREEMPT (RO)
//								
//					bit 22		ISRPENDING (RO)
//								interrupt pending flags, except NMI and Faults
//								0 = interrupt not pending
//								1 = interrupt pending 
//
//
//					bit 21-12		VECTPENDING (RO)
//								the interrupt number of the highest priority pending ISR 
//
//					bit 11		RETTOBASE (RO)
//								
//
//					bit 8-0		VECTACTIVE (RO)
//								active ISR number field 
//
//==========================================================================
#define ICSR_NMIPENDSET					(0x0001UL<<31)

#define ICSR_PENDSVSET					(0x0001UL<<28)
#define ICSR_PENDSVCLR					(0x0001UL<<27)

#define ICSR_PENDSTSET					(0x0001UL<<26)
#define ICSR_PENDSTCLR					(0x0001UL<<25)

#define ICSR_ISRPREEMPT					(0x0001UL<<23)
#define ICSR_ISRPENDING					(0x0001UL<<22)

#define ICSR_VECTPENDING				(0x03FFUL<<12)

#define ICSR_RETTOBASE					(0x0001UL<<11)
#define ICSR_VECTACTIVE					(0x01FFUL<<0)





//==========================================================================
// AIRCR (Application Interrupt and Reset Control Register)
//
//					addr = 0xE000_ED0C
//
//==========================================================================
//
//					bit 31-16		VECTKEY/VECTKEYSTAT
//								0x05FA	= VECTKEY
//								0xFA05	= VECTKEYSTAT
//
//					bit 15		ENDIANESS
//								0 = little endian
//								1 = big endian
//
//					bit 10-8		PRIGROUP
//
//					bit 2			SYSRESETREQ
//								causes a singal to be asserted to the outer system that indicates a reset is
//								requested. 
//
//					bit 1			VECTCLRACTIVE (self-clear)
//								clear active vecotor bit
//								0 = do not clear
//								1 = clear all state information for active NMI, Fault, and interrupts 
//
//					bit 0			VECTRESET (self-clear)
//								0 = do not reset system 
//								1 = reset system
//
//==========================================================================
#define AIRCR_VECTKEY					(0x05FAUL<<16)
#define AIRCR_VECTKEYSTAT				(0xFA05UL<<16)
#define AIRCR_VECTKEY_MASK				(0xFFFFUL<<16)

#define AIRCR_ENDIANESS_LITTLE_ENDIAN	(0x0000<<15)
#define AIRCR_ENDIANESS_BIG_ENDIAN		(0x0001<<15)

#define AIRCR_PRIGROUP_MASK				(0x0007<<8)

#define AIRCR_SYSRESETREQ				(0x0001<<2)
#define AIRCR_VECTCLRACTIVE				(0x0001<<1)
#define AIRCR_VECTRESET					(0x0001<<0)




//==========================================================================
// SCR (System Control Register)
//
//					addr = 0xE000_ED10
//
//==========================================================================
//
//					bit 4			SEVONPEND
//								
//					bit 2			SLEEPDEEP
//
//					bit 1			SLEEPONEXIT
//
//==========================================================================
#define SCR_SEVONPEND					(0x0001<<4)
#define SCR_SLEEPDEEP					(0x0001<<2)
#define SCR_SLEEPONEXIT					(0x0001<<1)




//==========================================================================
// CCR (Configuration Control Register)
//
//					addr = 0xE000_ED14
//
//==========================================================================
//
//					bit 9			STKALIGN
//								
//					bit 8			BFHFNMIGN
//
//					bit 4			DIV_0_TRP
//
//					bit 3			UNALIGN_TRP
//
//					bit 1			USERSETMPEND
//
//					bit 0			NONEBASETHRDENA
//
//==========================================================================
#define CCR_STKALIGN					(0x0001<<9)
#define CCR_BFHFNMIGN					(0x0001<<8)
#define CCR_DIV_0_TRP					(0x0001<<4)
#define CCR_UNALIGN_TRP					(0x0001<<3)
#define CCR_USERSETMPEND				(0x0001<<1)
#define CCR_NONEBASETHRDENA				(0x0001<<0)



//==========================================================================
// SHPR 0 (System Handler Priority Register 0)
//
//					addr = 0xE000_ED18
//
//==========================================================================
//
//					bit 31-24		PRI_7
//								
//					bit 23-16		PRI_6		Usgae Fault
//
//					bit 15-8		PRI_5		Bus Fault
//
//					bit 7-0		PRI_4		Memory Manage
//
//==========================================================================
#define PRIO_SHIFT_USAGE_FAULT		(16)
#define PRIO_SHIFT_BUS_FAULT		(8)
#define PRIO_SHIFT_MEMORY_MANAGE	(0)




//==========================================================================
// SHPR 1 (System Handler Priority Register 1)
//
//					addr = 0xE000_ED1C
//
//==========================================================================
//
//					bit 31-24		PRI_11		SVCALL
//								
//					bit 23-16		PRI_10
//
//					bit 15-8		PRI_9
//
//					bit 7-0		PRI_8
//
//==========================================================================
#define PRIO_SHIFT_SVCALL			(24)




//==========================================================================
// SHPR 2 (System Handler Priority Register 2)
//
//					addr = 0xE000_ED20
//
//==========================================================================
//
//					bit 31-24		PRI_15		SysTick
//								
//					bit 23-16		PRI_14		PendSV
//
//					bit 15-8		PRI_13
//
//					bit 7-0		PRI_12		Debug Monitor
//
//==========================================================================
#define PRIO_SHIFT_SYSTICK					(24)
#define PRIO_SHIFT_PENDSV					(16)
#define PRIO_SHIFT_DEBUG_MONITOR			(0)





//==========================================================================
// Interrupt Enable/Disable 
//
//					
//
//==========================================================================
#define SYSINT_ENABLE						(1)
#define SYSINT_DISABLE						(0)





//==========================================================================
//
// 	MACRO Definitions (System Control Space)
//
//==========================================================================
#define CSP_SCS_GET_ICTR(scs)					((scs)->ICTR)
//-----------------------------------------------------------------------------------------
#define CSP_SCS_GET_ACR(scs)					((scs)->ACR)
#define CSP_SCS_SET_ACR(scs, val)				((scs)->ACR = (val))
//-----------------------------------------------------------------------------------------


//==========================================================================
//
// 	MACRO Definitions (SysTick)
//
//==========================================================================
#define CSP_SYSTICK_GET_CSR(systick)			((systick)->CSR)
#define CSP_SYSTICK_SET_CSR(systick, val)		((systick)->CSR = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SYSTICK_GET_RVR(systick)			((systick)->RVR)
#define CSP_SYSTICK_SET_RVR(systick, val)		((systick)->RVR = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SYSTICK_GET_CVR(systick)			((systick)->CVR)
#define CSP_SYSTICK_SET_CVR(systick, val)		((systick)->CVR = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SYSTICK_GET_CALIB(systick)			((systick)->CALIB)
//-----------------------------------------------------------------------------------------


//==========================================================================
//
// 	MACRO Definitions (NVIC)
//
//==========================================================================
#define CSP_NVIC_GET_ISER(nvic, index)			((nvic)->ISER[(index)])
#define CSP_NVIC_SET_ISER(nvic, index, val)		((nvic)->ISER[(index)] = (val))
//-----------------------------------------------------------------------------------------
#define CSP_NVIC_GET_ICER(nvic, index)			((nvic)->ICER[(index)])
#define CSP_NVIC_SET_ICER(nvic, index, val)		((nvic)->ICER[(index)] = (val))
//-----------------------------------------------------------------------------------------
#define CSP_NVIC_GET_ISPR(nvic, index)			((nvic)->ISPR[(index)])
#define CSP_NVIC_SET_ISPR(nvic, index, val) 	((nvic)->ISPR[(index)] = (val))
//-----------------------------------------------------------------------------------------
#define CSP_NVIC_GET_ICPR(nvic, index)			((nvic)->ICPR[(index)])
#define CSP_NVIC_SET_ICPR(nvic, index, val) 	((nvic)->ICPR[(index)] = (val))
//-----------------------------------------------------------------------------------------
#define CSP_NVIC_GET_IABR(nvic, index)			((nvic)->IABR[(index)])
//-----------------------------------------------------------------------------------------
#define CSP_NVIC_GET_IPR(nvic, irq)				((nvic)->IPR[(irq)])
#define CSP_NVIC_SET_IPR(nvic, irq, val) 		((nvic)->IPR[(irq)] = (val))
//-----------------------------------------------------------------------------------------


//==========================================================================
//
// 	MACRO Definitions (SCB)
//
//==========================================================================
#define CSP_SCB_GET_CPUID(scb)					((scb)->CPUID)
//-----------------------------------------------------------------------------------------
#define CSP_SCB_GET_ICSR(scb)					((scb)->ICSR)
#define CSP_SCB_SET_ICSR(scb, val)				((scb)->ICSR = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCB_GET_AIRCR(scb)					((scb)->AIRCR)
#define CSP_SCB_SET_AIRCR(scb, val)				((scb)->AIRCR = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCB_GET_SCR(scb)					((scb)->SCR)
#define CSP_SCB_SET_SCR(scb, val)				((scb)->SCR = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCB_GET_CCR(scb)					((scb)->CCR)
#define CSP_SCB_SET_CCR(scb, val)				((scb)->CCR = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCB_GET_SHPR2(scb)					((scb)->SHPR2)
#define CSP_SCB_SET_SHPR2(scb, val)				((scb)->SHPR2 = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCB_GET_SHCSR3(scb)					((scb)->SHPR3)
#define CSP_SCB_SET_SHCSR3(scb, val)			((scb)->SHPR3 = (val))
//-----------------------------------------------------------------------------------------


//==========================================================================
//
// 	MACRO Definitions (TPIU)
//
//==========================================================================
#define CSP_TPIU_GET_SSPSR(tpiu)				((tpiu)->SSPSR)
//-----------------------------------------------------------------------------------------
#define CSP_TPIU_GET_CSPSR(tpiu)				((tpiu)->CSPSR)
#define CSP_TPIU_SET_CSPSR(tpiu, val)			((tpiu)->CSPSR = (val))
//-----------------------------------------------------------------------------------------
#define CSP_TPIU_GET_ACPR(tpiu)					((tpiu)->ACPR)
#define CSP_TPIU_SET_ACPR(tpiu, val)			((tpiu)->ACPR = (val))
//-----------------------------------------------------------------------------------------
#define CSP_TPIU_GET_SPPR(tpiu)					((tpiu)->SPPR)
#define CSP_TPIU_SET_SPPR(tpiu, val)			((tpiu)->SPPR = (val))
//-----------------------------------------------------------------------------------------


extern CSP_SCS_T			* const			SCS; 
extern CSP_SYSTICK_T 		* const			SYSTICK; 
extern CSP_NVIC_T			* const			NVIC; 
extern CSP_SCB_T			* const			SCB; 
extern CSP_TPIU_T			* const 		TPIU; 





//==========================================================================
//
// 	S Y S T I C K    F U N C T I O N S  
//
//==========================================================================
void CSP_SysTick_Init (CSP_SYSTICK_T * const systick, UINT32 clk_src, UINT32 ext_ref, UINT32 ext_div, UINT32 reload); 
void CSP_SysTick_Run (CSP_SYSTICK_T * const systick);
void CSP_SysTick_ConfigureInterrupt (CSP_SYSTICK_T * const systick, UINT32 intr_mask, UINT32 enable);  

void CSP_SCB_Set_PriorityGroup (CSP_SCB_T * const scb, UINT32 priority_group); 
void CSP_NVIC_ConfigureInterrupt (CSP_NVIC_T * const nvic, NVIC_IntrConfig * nvic_config); 



#endif 


